FIG. 10 is a perspective view illustrating a prior art HBT. In the figure, an HBT 200 includes a GaAs substrate 201 which is produced by a liquid encapsulated Czochralski method (hereinafter referred to as LEC). A buffer layer 201a about 1 .mu.m thick is disposed on the GaAs substrate 201. The buffer layer 201a comprises an intrinsic type (hereinafter referred to as i type) GaAs/A1GaAs superlattice layer about 800 nm thick and an i type GaAs layer about 200 nm thick layer. A collector contact layer 211 is disposed on the buffer layer 201a. A collector layer 212 is disposed on a center part of the collector contact layer 211, and collector electrodes 210 comprising three layers of AuGe/Ni/Au are disposed on the collector contact layer 211 at opposite sides of and spaced apart from the collector layer 212. The collector contact layer 211 comprises an n.sup.+ type GaAs layer having a thickness of 500 nm and a dopant concentration of 5.times.10.sup.18 cm.sup.-3, and the collector layer 212 comprises an n type GaAs layer having a thickness of 500 nm and a dopant concentration of 5.times.10.sup.16 cm.sup.-3.
A p.sup.+ type AlGaAs base layer 221 is disposed on the collector layer 212. The base layer 221 has a thickness of 100 nm and a dopant concentration of 1.about.4.times.10.sup.19 cm.sup.-3. An n type AlGaAs emitter layer 231 is disposed on a center part of the base layer 221. The emitter layer 231 has a thickness of 150 nm and a dopant concentration of 5.times.10.sup.17 cm.sup.-3. Base electrodes 220 comprising three layers of Ti/Ni/Au are disposed on the base layer 221 at opposite sides of and spaced apart from the emitter layer 231. In the AlGaAs base layer 221, the ratio of AlAs mixed crystal gradually increases upward from 0 to 0.1. The emitter layer 231 comprises three AlGaAs layers, i.e., an AlGaAs layer grown on the base layer 221 with the AlAs mixed crystal ratio gradually increasing upward from 0.1 to 0.3, an Al.sub.0.3 Ga.sub.0.7 As layer grown thereon to a prescribed thickness, and an AlGaAs layer grown thereon with the AlAs mixed crystal ratio gradually decreasing upward from 0.3 to 0.
An n.sup.+ type InGaAs emitter contact layer is disposed on the emitter layer 231. The emitter contact layer 232 has a thickness of 100 nm and a dopant concentration of 4.times.10.sup.19 cm.sup.-3. An emitter electrode 230 comprising three layers of Ti/Mo/Au is disposed on the emitter contact layer 232. In the emitter contact layer 232, the ratio of InAs mixed crystal gradually increases upward from 0 to 0.5. Since the emitter contact layer 232 reduces the contact resistance between the emitter layer 231 and the emitter electrode 230, InGaAs having a low contact resistance with the emitter electrode 230 and a low sheet resistivity is employed as the emitter contact layer 232. Insulating regions 202 contact the opposite sides of the collector contact layer 211 and reach the surface of the buffer layer 201a. Insulating regions 203 contact opposite sides of the base layer 221 and the collector layer 212.
A method for manufacturing the HBT of FIG. 10 is illustrated in FIGS. 11(a)-11(f) and 12(a)-12(f).
Initially, an i type GaAs layer 201a about 1 .mu.m thick, an n.sup.+ type GaAs layer 211 about 500 nm thick, and an n type GaAs layer 212a about 500 nm thick are successively grown on the GaAs substrate 201. Thereafter, a p.sup.+ type AlGaAs layer 221a is epitaxially grown on the n type GaAs layer 212a to a thickness of 100 nm while gradually increasing the ratio of AlAs mixed crystal from 0 to 0.1.
Then, an AlGaAs layer is epitaxially grown on the p.sup.+ type AlGaAs layer 221a in the following manner. That is, in the initial stage of the epitaxial growth, the AlGaAs layer is grown while gradually increasing the AlAs mixed crystal ratio from 0.1 to 0.3 until a prescribed thickness is achieved and, thereafter, the AlGaAs layer is grown while maintaining the AlAs mixed crystal ratio at 0.3 until a prescribed thickness is achieved and, finally, the AlGaAs layer is grown while gradually decreasing the AlAs mixed crystal ratio from 0.3 to 0, completing an n type AlGaAs graded layer 231a having a thickness of 150 nm.
Then, an n.sup.+ type InGaAs layer is epitaxially grown on the AlGaAs graded layer 231a while gradually increasing the InAs mixed crystal ratio from 0 to 0.5, forming an n.sup.+ type InGaAs graded layer 232a having a thickness of 100 nm (FIG. 11(a)).
Thereafter, using a first photoresist film 205a having a prescribed pattern as a mask, protons are implanted, reaching the boundary between the n type GaAs layer 212a and the n.sup.+ type GaAs layer 211, forming first insulating regions 203 (FIG. 11(b)). Then, using a second photoresist film 205b as a mask, protons are implanted, reaching into the buffer layer 201a, forming second insulating regions 202 (FIG. 11(c)).
Thereafter, a dummy emitter 241 comprising an insulating film is formed on a part of the InGaAs layer 232a, and a mask pattern 242 comprising WSi or Au and wider than the dummy emitter 241 is formed on the dummy emitter 241 (FIG. 11(d)). The mask pattern 242 is used in a subsequent lift-off process. Using the dummy emitter 241 as a mask, the n.sup.+ InGaAs layer 232a is etched to form an emitter contact layer 232 (FIG. 11(e)).
Then, a photoresist film is deposited and patterned to form a third photoresist pattern 205c having an aperture around the dummy emitter 241. Using the photoresist pattern 205c as a mask, the n type AlGaAs layer 231a is selectively etched to from an emitter layer 231. Thereafter, a base metal layer 220a is deposited over the entire surface (FIG. 11(f)), and the photoresist pattern 205c and overlying portions of the base metal layer 220a are removed by a lift-off technique, leaving base electrodes 220 (FIG. 12(a)).
Then, a fourth photoresist film 205d is deposited over the entire surface so that the upper surface of the photoresist film 205d reaches the lower surface of the mask pattern 242. Using the photoresist film 205d as a mask, the dummy emitter 241, the mask pattern 242, and the base metal 220a are removed (FIG. 12(b)).
Then, an emitter metal 230a is deposited over the entire surface (FIG. 12(c)), and the fourth photoresist film 205d and overlying portions of the emitter metal 230a are removed by a lift-off technique, leaving an emitter electrode 230 (FIG. 12(d)).
Thereafter, two grooves are formed penetrating through portions of the n type AlGaAs graded layer 231a, p.sup.+ type AlGaAs layer 221a, and n type GaAs layer 212a at opposite sides of the emitter electrode 230, and collector electrodes 210 are formed in the respective grooves (FIG. 12(e)).
Finally, a surface protection film 206 is formed over the entire surface, and portions of the surface protection film 206 on the collector electrodes 210 are removed to form apertures 206a. Then, a wiring layer 207 is formed on the surface protection film 206 so that the wiring layer 207 is in contact with the collector electrodes 210 through the apertures 206a of the surface protection film 206 (FIG. 12(f)). The spaced apart portions of the wiring layer 207 in contact with the respective collector electrodes 210 at opposite sides of the collector layer 212 are connected to each other by an air bridge wiring 207a.
A problem in manufacturing the HBT resides in the process of growing the n.sup.+ type In.sub.y Ga.sub.1-y As layer 232a (emitter contact layer 232) on the n type Al.sub.y Ga.sub.1-y As (y: 0.1.about.0.3.about.0) graded layer 231a (emitter layer 231), i.e., on a GaAs layer.
A description is given of the problem in the growth of an In.sub.y Ga.sub.1-y As layer (y: 0.about.1.0) on a GaAs layer, which layers have different lattice constants, to a prescribed thickness that provides a sufficiently low contact resistance.
FIGS. 13(a)-13(b) are diagrams for explaining a GaAs crystal lattice and an InAs crystal lattice, respectively, and FIG. 13(c) is a graph illustrating lattice constant (a) vs. energy band gap (EG) characteristics of AlGaAs and InGaAs which are typical III-V mixed crystal semiconductors. In FIG. 13(a), a unit cell of the crystal lattice of GaAs (hereinafter referred to as GaAs crystal) 10a comprises As atoms 11 and Ga atoms 12 and has a lattice constant of 5.6535 .ANG.. In FIG. 13(b), a unit cell of the crystal lattice of InAs (hereinafter referred to as InAs crystal) 10b comprises As atoms 11 and In atoms 13 and has a lattice constant of 6.0584 .ANG..
The III-V compound semiconductors include mixed crystal semiconductors comprising three elements, such as AlGaAs and InGaAs, besides the above-described compound semiconductors comprising two elements. In these ternary compound semiconductors, the energy band gap (EG) can be continuously varied by varying the AlAs or InAs crystal ratio. AlGaAs is especially favorable as a constituent of a semiconductor device because the lattice constant of AlGaAs do not vary with the variation of the AlAs mixed crystal ratio. However, the energy band gap of AlGaAs is larger than that of GaAs. On the other hand, the energy band gap of InGaAs is smaller than that of GaAs. Therefore, for the purpose of reducing the resistance of a semiconductor layer included in a device, InGaAs has an advantage over GaAs.
However, the lattice constant of InGaAs having an InAs mixed crystal ratio of 1, i.e., the lattice constant a.sub.2 of the InAs crystal, is different from the lattice constant a.sub.1 of the GaAs crystal by 7.2%. Therefore, a coherent single crystal is not attained due to dislocations when an In.sub.y Ga.sub.1-y As layer is grown on a GaAs layer. In FIG. 14(a), a crystal structure of a monocrystalline In.sub.O.5 Ga.sub.1-0.5 As layer 20b (lattice constant a.sub.12) is compared with a crystal structure of a monocrystalline GaAs layer 20a (lattice constant a.sub.1).
As shown in FIG. 14(b), when the thickness T.sub.1 of the InGaAs layer 20b is small, the lattice mismatch generated by the dislocations of the crystal lattice is eased by the strain of the crystal lattice, and a pseudomorphic crystal structure is attained. Therefore, the monocrystalline InGaAs layer 20b can be grown on the GaAs layer 20a.
On the other hand, in the crystal growth of InGaAs, segregation of In atoms, i.e., escape of In atoms in the InGaAs layer 20b toward the surface of the layer (FIG. 15(a)), or loss of In atoms occurs, resulting in a crystal defect that facilitates dislocations. If the thickness of In.sub.y Ga.sub.1-y As having a lattice constant that does not match with the lattice constant of GaAs exceeds a critical thickness T.sub.O, a dislocation 22 is produced by the crystal defect, and the strain of the InGaAs crystal is relaxed. As a result, the pseudomorphic structure is destroyed in a part 21b.sub.1 exceeding the critical thickness T.sub.O of the In.sub.y Ga.sub.1-y As layer 21b grown on the GaAs layer 20a as shown in FIG. 15(b), and incoherent or polycrystalline InGaAs is grown. Further, in such a crystal growth, the segregation of In atoms and the loss of In atoms are facilitated, so that a favorable surface morphology of the InGaAs layer is not attained.
As shown in FIG. 16, the critical thickness T.sub.O of the InGaAs layer decreases with an increase in the InAs mixed crystal ratio (y) of the InGaAs layer. For example, the critical thicknesses at InAs mixed crystal ratios of 0.15 and 0.2 are 250 .ANG. and 200 .ANG., respectively. If the critical crystal thickness is exceeded, pseudomorphic crystal growth is impossible.
Therefore, if an InGaAs layer grown on a GaAs layer to a thickness exceeding the critical thickness T.sub.O is applied to an HBT, fine patterns of insulating films and conductive films cannot be formed on the InGaAs layer with high reproducibility because of the rough surface of the InGaAs layer.
This problem will be described concretely.
For example, when the dummy emitter 241 is formed by patterning an insulating film in the above-described HBT production process, if the insulating film 241a and the metal layer 242a are formed on the n.sup.+ type InGaAs layer 232a having a rough surface, as shown in FIG. 17(a), the rough surface of the InGaAs layer 232a adversely affects the surface morphologies of the insulating film 241a and the metal layer 242a.
If a photoresist film is deposited and patterned on the metal layer 242a, the side surface 215 of the patterned photoresist film 205 is rough due to the irregular reflection of light used to expose the film (FIG. 17(a)). When the metal layer 242a and the insulating film 241a are patterned using the photoresist pattern 205 as a mask, the side surfaces 42 and 41 of the patterned metal layer 242 and the patterned insulating dummy emitter 241, respectively, are rough because of the rough side surface 215 of the photoresist pattern 205 and the rough surfaces of the metal layer 242a and the insulating film 241a (FIG. 17(b)). Therefore, a fine dummy emitter is not attained, which makes it difficult to form a fine emitter.
While in the above-described HBT production process the space between the emitter layer 231 and the base electrode 220 depends on the width of the over-hanging portion of the metal film 242 on the dummy emitter 241 (FIG. 11(d)), a side wall may be interposed between the emitter layer 231 and the base electrode 220. In this case, however, it is difficult to form the side wall.
FIG. 18 is a sectional view illustrating an HBT including side walls 235 interposed between the emitter layer 231 and the respective base electrodes 220. In FIG. 18, the same reference numerals as in FIG. 10 designate the same or corresponding parts. These side walls 235 contact the opposite side surfaces of the GaAs emitter layer 231 and the InGaAs emitter contact layer 232, after the formation of these layers, and serve as a mask for patterning the emitter electrode 230. After the device is completed, these side walls 235 serve as insulators between the respective base electrodes 220 and the emitter electrode 30. Further, since the portions of the base layer 221 between the emitter layer 231 and the respective base electrodes 220 are covered with the side walls 235, surface recombination current at these portions is reduced.
In the production of the HBT shown in FIG. 18, if the surface morphology of the InGaAs layer that is to be the emitter contact layer 232 is rough, a photoresist film formed on the InGaAs layer for patterning of the emitter layer and the emitter contact layer has rough side surfaces, with a result that the side walls are not favorably formed on the side surfaces of the emitter layer and the emitter contact layer.
As described above, in the crystal structure formed by growing an InGaAs layer on a GaAs layer, a favorable surface morphology of the InGaAs layer is not achieved. If such a crystal structure is applied to a device, such as an HBT, it is difficult to form a fine pattern on the InGaAs layer.
Meanwhile, Japanese Published Patent Application No. Hei. 3-280419 discloses a method for growing an n type InGaAs layer on a GaAs layer. In this prior art Publication, in order to avoid degradation of the surface morphology of the InGaAs layer, the InGaAs layer is grown at a low temperature. However, in the low temperature growth for improving the surface morphology, a crystal structure of good quality is not attained, whereby the contact resistance between the semiconductor layer and the metal layer and the sheet resistivity unfavorably increases. In addition, uniformity in the contact resistivity and the sheet resistivity in a wafer are reduced.
Japanese Published Patent Application No. Hei. 4-72740 discloses an ohmic electrode comprising a superlattice layer disposed on a GaAs substrate and a metal layer disposed on the superlattice layer. The superlattice layer comprises alternating n type In.sub.x Ga.sub.1-x As layers and n type In.sub.y Ga.sub.1-y As layers, in which both of the indium composition ratios x and y gradually increase upward while maintaining the relation of x&lt;y, and the n type In.sub.y Ga.sub.1-y As layer is present at the top of the superlattice layer, whereby dislocation in the superlattice layer are suppressed and a low resistance ohmic contact is realized. In this structure, however, compositions of the n type In.sub.x Ga.sub.1-x As layer and the n type In.sub.y Ga.sub.1-y As layer must be precisely controlled. Furthermore, since the compositions of these layers are gradually varied, an interface having a large difference in lattice constants is not present in the superlattice layer. Therefore, the segregation of In atoms that causes the rough surface morphology is not effectively prevented.
Further, Japanese Published Patent Application No. Sho. 63-186416 discloses a compound semiconductor substrate comprising an Si substrate and a high electron mobility compound semiconductor layer, such as GaAs, grown on the Si substrate. The compound semiconductor layer comprises alternating In.sub.0.3 Ga.sub.0.7 As layers and GaAs layers which prevent dislocation at the interface between the substrate and the compound semiconductor layer from spreading in the compound semiconductor layer, and the thickness of each layer of the alternating compound semiconductor layers is larger than the critical thickness, whereby the quality of the compound semiconductor layer is improved. In addition, an increase in the thickness improves reproducibility. In the alternating compound semiconductor layers, however, the GaAs layer having an energy band gap larger than that of the In.sub.0.3 Ga.sub.0.7 As layer is as thick as 500 .ANG., so that the sheet resistivity of the alternating layers is significantly increased due to the GaAs layer. Therefore, this structure is unfavorable to an improvement of device characteristics.
Further, Japanese Published Patent Application No. Sho. 63-156356 discloses a pnp bipolar transistor including an emitter layer of a strained superlattice structure in which a plurality of p type InGaAs layers of large lattice constant and small energy band gap and a plurality of p type GaAs layers of small lattice constant and large energy band gap are alternatingly laminated, whereby the effective mass of holes in the emitter layer is reduced to realize an operating speed as high as that of an npn transistor.
However, in the strained superlattice structure, two layers of different lattice constants, i.e., the InGaAs layer and the GaAs layer, are in the pseudomorphic state, so that this structure is not for preventing the degradation of surface morphology of a lattice mismatch lamination structure.
As described above, in the conventional crystal structure in which an In.sub.y Ga.sub.1-y As layer is grown on a GaAs layer, if the epitaxial growth is carried out at a low temperature to improve the surface morphology, the contact resistivity and the sheet resistivity are unfavorably increased and the uniformities of these resistivities in a wafer are reduced. On the contrary, if the epitaxial growth is carried out at a high temperature to avoid these problems, segregation and loss of In atoms adversely affect the surface morphology. Accordingly, the crystal growth of InGaAs on GaAs has been a problem in realizing a high-performance HBT.